In a semiconductor integrated circuit, a desired electronic circuit is composed of a combination of a resistance element, a capacitor, a transistor, and the like. Therefore, it is desirable that the characteristic of each element should not be changed. Taking an example of a resistance element, a change in the resistance value of the resistance element is highly undesirable for the configuration of an electronic circuit. Lots of resistance elements, however, use polysilicon or a diffusion layer as a material. The widening state of the depletion layer is therefore changed by a potential difference between the potential of the resistance element and the potential of a neighboring (upper or lower surface) semiconductor substrate or the like, thereby changing the width of a conductive region.
This changes the resistance value of the resistance element.
In order to suppress such a change in the resistance value caused by the potential of the neighboring semiconductor substrate or the like, Patent Document 1 describes a semiconductor device (resistance element) 100 as shown in FIG. 8.
In this semiconductor device 100, a P-type diffusion region 103 is formed on the main surface of an N-type island region 102 formed in a P-type semiconductor substrate 101. On this surface, there are provided a first electrode 104 for applying a high-potential voltage and a second electrode 105 for applying a low-potential voltage, and in addition, a third electrode 106 for applying a high-potential voltage on the surface of the island region 102 at the outside of the surface of the P-type diffusion region 103 and a fourth electrode 107 for applying a low-potential voltage thereon.
With such a configuration, the semiconductor device 100 is configured such that the electric potential distribution of the island region 102 corresponds to that of the P-type diffusion region 103.
Additionally, Patent Document 2 describes a semiconductor device (resistance element) 200 as shown in FIG. 9.
This semiconductor device 200 includes: an epitaxial layer 202 formed on a semiconductor substrate 201; a buried layer 203 formed in the epitaxial layer 202; a circular element isolation region 204 having an approximately same depth as that of the buried layer 203 and spaced apart from the buried layer 203; and an N+ type layer 205 formed in the circular element isolation region 204 from the surface of the epitaxial layer 202.
On the uppermost surface, a LOCOS oxide film 206, a polysilicon resistance 207, and an interlayer insulation layer 208 are successively provided, and electrodes 210 to 212 are arranged at three places in the interlayer insulation layer 208 on the polysilicon resistance 207. Furthermore, an electrode 213 is formed on the N+ type layer 205. In this situation, the three electrodes 210 to 212 are disposed such that the electrode 212 is located substantially at a center position on the polysilicon resistance 207 to have the same distances from the electrodes 210 and 211, respectively. The electrode 212 and the electrode 213 are connected by a wiring 209 to maintain the same potential.